|
SingingCat 0
application
|
SX126x register definitions. More...
Go to the source code of this file.
Macros | |
| #define | SX126X_REG_ANA_LNA 0x08E2 |
| #define | SX126X_REG_ANA_MIXER 0x08E5 |
| #define | SX126X_REG_BITBANG_A_REG 0x0680 |
| TX bitbang A. More... | |
| #define | SX126X_REG_BITBANG_A_REG_ENABLE_MASK (0x07UL << SX126X_REG_BITBANG_A_REG_ENABLE_POS) |
| #define | SX126X_REG_BITBANG_A_REG_ENABLE_POS (4U) |
| #define | SX126X_REG_BITBANG_A_REG_ENABLE_VAL (0x01UL << SX126X_REG_BITBANG_A_REG_ENABLE_POS) |
| #define | SX126X_REG_BITBANG_B_REG 0x0587 |
| TX bitbang B. More... | |
| #define | SX126X_REG_BITBANG_B_REG_ENABLE_MASK (0x0FUL << SX126X_REG_BITBANG_B_REG_ENABLE_POS) |
| #define | SX126X_REG_BITBANG_B_REG_ENABLE_POS (0U) |
| #define | SX126X_REG_BITBANG_B_REG_ENABLE_VAL (0x0CUL << SX126X_REG_BITBANG_B_REG_ENABLE_POS) |
| #define | SX126X_REG_CRCPOLYBASEADDRESS 0x06BE |
| The address of the register holding the first byte defining the CRC polynomial. More... | |
| #define | SX126X_REG_CRCSEEDBASEADDRESS 0x06BC |
| The address of the register holding the first byte defining the CRC seed. More... | |
| #define | SX126X_REG_EVT_CLR 0x0944 |
| Event clear. More... | |
| #define | SX126X_REG_EVT_CLR_TIMEOUT_MASK (0x01UL << SX126X_REG_EVT_CLR_TIMEOUT_POS) |
| #define | SX126X_REG_EVT_CLR_TIMEOUT_POS (1U) |
| #define | SX126X_REG_IN_EN_REG 0x0583 |
| Input enable. More... | |
| #define | SX126X_REG_IN_EN_REG_DIO3_MASK (0x01UL << SX126X_REG_IN_EN_REG_DIO3_POS) |
| #define | SX126X_REG_IN_EN_REG_DIO3_POS (3U) |
| #define | SX126X_REG_IRQ_POLARITY 0x0736 |
| WORKAROUND - Optimizing the Inverted IQ Operation, see DS_SX1261-2_V1.2 datasheet chapter 15.4. More... | |
| #define | SX126X_REG_LR_SYNCH_TIMEOUT 0x0706 |
| Number of symbols given as SX126X_REG_LR_SYNCH_TIMEOUT[7:3] * 2 ^ (2*SX126X_REG_LR_SYNCH_TIMEOUT[2:0] + 1) More... | |
| #define | SX126X_REG_LR_SYNCWORD 0x0740 |
| The addresses of the register holding LoRa Modem SyncWord value 0x1424: LoRaWAN private network, 0x3444: LoRaWAN public network. More... | |
| #define | SX126X_REG_OCP 0x08E7 |
| Set the current max value in the over current protection. More... | |
| #define | SX126X_REG_OUT_DIS_REG 0x0580 |
| Output disable. More... | |
| #define | SX126X_REG_OUT_DIS_REG_DIO3_MASK (0x01UL << SX126X_REG_OUT_DIS_REG_DIO3_POS) |
| #define | SX126X_REG_OUT_DIS_REG_DIO3_POS (3U) |
| #define | SX126X_REG_PKTPARAMS 0x0704 |
| The address of the register holding the packet configuration. More... | |
| #define | SX126X_REG_RNGBASEADDRESS 0x0819 |
| #define | SX126X_REG_RTC_CTRL 0x0902 |
| RTC control. More... | |
| #define | SX126X_REG_RX_ADDRESS_POINTER 0x0803 |
| RX address pointer. More... | |
| #define | SX126X_REG_RXGAIN 0x08AC |
| #define | SX126X_REG_RXTX_PAYLOAD_LEN 0x06BB |
| RX/TX payload length. More... | |
| #define | SX126X_REG_SYNCWORDBASEADDRESS 0x06C0 |
| The addresses of the registers holding SyncWords values. More... | |
| #define | SX126X_REG_TX_CLAMP_CFG 0x08D8 |
| WORKAROUND - Better resistance to antenna mismatch, see DS_SX1261-2_V1.2 datasheet chapter 15.2. More... | |
| #define | SX126X_REG_TX_CLAMP_CFG_MASK (0x0FUL << SX126X_REG_TX_CLAMP_CFG_POS) |
| #define | SX126X_REG_TX_CLAMP_CFG_POS (1U) |
| #define | SX126X_REG_TX_MODULATION 0x0889 |
| WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see DS_SX1261-2_V1.2 datasheet chapter 15.1. More... | |
| #define | SX126X_REG_WHITSEEDBASEADDRESS 0x06B8 |
| The address of the register holding the first byte defining the whitening seed. More... | |
| #define | SX126X_REG_XTATRIM 0x0911 |
| Change the value on the device internal trimming capacitor. More... | |
SX126x register definitions.
Revised BSD License Copyright Semtech Corporation 2020. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL SEMTECH CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file sx126x_regs.h.
| #define SX126X_REG_ANA_LNA 0x08E2 |
The address of the register used to disable the LNA
Definition at line 90 of file sx126x_regs.h.
| #define SX126X_REG_ANA_MIXER 0x08E5 |
The address of the register used to disable the mixer
Definition at line 95 of file sx126x_regs.h.
| #define SX126X_REG_BITBANG_A_REG 0x0680 |
TX bitbang A.
Definition at line 170 of file sx126x_regs.h.
| #define SX126X_REG_BITBANG_A_REG_ENABLE_MASK (0x07UL << SX126X_REG_BITBANG_A_REG_ENABLE_POS) |
Definition at line 172 of file sx126x_regs.h.
| #define SX126X_REG_BITBANG_A_REG_ENABLE_POS (4U) |
Definition at line 171 of file sx126x_regs.h.
| #define SX126X_REG_BITBANG_A_REG_ENABLE_VAL (0x01UL << SX126X_REG_BITBANG_A_REG_ENABLE_POS) |
Definition at line 173 of file sx126x_regs.h.
| #define SX126X_REG_BITBANG_B_REG 0x0587 |
TX bitbang B.
Definition at line 178 of file sx126x_regs.h.
| #define SX126X_REG_BITBANG_B_REG_ENABLE_MASK (0x0FUL << SX126X_REG_BITBANG_B_REG_ENABLE_POS) |
Definition at line 180 of file sx126x_regs.h.
| #define SX126X_REG_BITBANG_B_REG_ENABLE_POS (0U) |
Definition at line 179 of file sx126x_regs.h.
| #define SX126X_REG_BITBANG_B_REG_ENABLE_VAL (0x0CUL << SX126X_REG_BITBANG_B_REG_ENABLE_POS) |
Definition at line 181 of file sx126x_regs.h.
| #define SX126X_REG_CRCPOLYBASEADDRESS 0x06BE |
The address of the register holding the first byte defining the CRC polynomial.
Definition at line 58 of file sx126x_regs.h.
| #define SX126X_REG_CRCSEEDBASEADDRESS 0x06BC |
The address of the register holding the first byte defining the CRC seed.
Definition at line 53 of file sx126x_regs.h.
| #define SX126X_REG_EVT_CLR 0x0944 |
Event clear.
Definition at line 139 of file sx126x_regs.h.
| #define SX126X_REG_EVT_CLR_TIMEOUT_MASK (0x01UL << SX126X_REG_EVT_CLR_TIMEOUT_POS) |
Definition at line 141 of file sx126x_regs.h.
| #define SX126X_REG_EVT_CLR_TIMEOUT_POS (1U) |
Definition at line 140 of file sx126x_regs.h.
| #define SX126X_REG_IN_EN_REG 0x0583 |
Input enable.
Definition at line 163 of file sx126x_regs.h.
| #define SX126X_REG_IN_EN_REG_DIO3_MASK (0x01UL << SX126X_REG_IN_EN_REG_DIO3_POS) |
Definition at line 165 of file sx126x_regs.h.
| #define SX126X_REG_IN_EN_REG_DIO3_POS (3U) |
Definition at line 164 of file sx126x_regs.h.
| #define SX126X_REG_IRQ_POLARITY 0x0736 |
WORKAROUND - Optimizing the Inverted IQ Operation, see DS_SX1261-2_V1.2 datasheet chapter 15.4.
Definition at line 117 of file sx126x_regs.h.
| #define SX126X_REG_LR_SYNCH_TIMEOUT 0x0706 |
Number of symbols given as SX126X_REG_LR_SYNCH_TIMEOUT[7:3] * 2 ^ (2*SX126X_REG_LR_SYNCH_TIMEOUT[2:0] + 1)
Definition at line 186 of file sx126x_regs.h.
| #define SX126X_REG_LR_SYNCWORD 0x0740 |
The addresses of the register holding LoRa Modem SyncWord value 0x1424: LoRaWAN private network, 0x3444: LoRaWAN public network.
Definition at line 80 of file sx126x_regs.h.
| #define SX126X_REG_OCP 0x08E7 |
Set the current max value in the over current protection.
Definition at line 112 of file sx126x_regs.h.
| #define SX126X_REG_OUT_DIS_REG 0x0580 |
Output disable.
Definition at line 156 of file sx126x_regs.h.
| #define SX126X_REG_OUT_DIS_REG_DIO3_MASK (0x01UL << SX126X_REG_OUT_DIS_REG_DIO3_POS) |
Definition at line 158 of file sx126x_regs.h.
| #define SX126X_REG_OUT_DIS_REG_DIO3_POS (3U) |
Definition at line 157 of file sx126x_regs.h.
| #define SX126X_REG_PKTPARAMS 0x0704 |
The address of the register holding the packet configuration.
Definition at line 68 of file sx126x_regs.h.
| #define SX126X_REG_RNGBASEADDRESS 0x0819 |
The address of the register giving a 32-bit random number
Definition at line 85 of file sx126x_regs.h.
| #define SX126X_REG_RTC_CTRL 0x0902 |
RTC control.
Definition at line 134 of file sx126x_regs.h.
| #define SX126X_REG_RX_ADDRESS_POINTER 0x0803 |
RX address pointer.
Definition at line 146 of file sx126x_regs.h.
| #define SX126X_REG_RXGAIN 0x08AC |
The address of the register holding RX Gain value 0x94: power saving, 0x96: rx boosted
Definition at line 102 of file sx126x_regs.h.
| #define SX126X_REG_RXTX_PAYLOAD_LEN 0x06BB |
RX/TX payload length.
Definition at line 151 of file sx126x_regs.h.
| #define SX126X_REG_SYNCWORDBASEADDRESS 0x06C0 |
The addresses of the registers holding SyncWords values.
Definition at line 73 of file sx126x_regs.h.
| #define SX126X_REG_TX_CLAMP_CFG 0x08D8 |
WORKAROUND - Better resistance to antenna mismatch, see DS_SX1261-2_V1.2 datasheet chapter 15.2.
Definition at line 127 of file sx126x_regs.h.
| #define SX126X_REG_TX_CLAMP_CFG_MASK (0x0FUL << SX126X_REG_TX_CLAMP_CFG_POS) |
Definition at line 129 of file sx126x_regs.h.
| #define SX126X_REG_TX_CLAMP_CFG_POS (1U) |
Definition at line 128 of file sx126x_regs.h.
| #define SX126X_REG_TX_MODULATION 0x0889 |
WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see DS_SX1261-2_V1.2 datasheet chapter 15.1.
Definition at line 122 of file sx126x_regs.h.
| #define SX126X_REG_WHITSEEDBASEADDRESS 0x06B8 |
The address of the register holding the first byte defining the whitening seed.
Definition at line 63 of file sx126x_regs.h.
| #define SX126X_REG_XTATRIM 0x0911 |
Change the value on the device internal trimming capacitor.
Definition at line 107 of file sx126x_regs.h.
1.9.4